1. Field of the Invention
The present invention relates to an output circuit for a series regulator or a power amplifier, and more particularly, to an output circuit in which an NPN transistor or an NMOS transistor is used as an output transistor.
2. Prior Art
A PMOS transistor is frequently used as an output transistor in a series regulator as typified by an LDO (low drop out regulator) or a power amplifier that supplies a controlled voltage to a load circuit. However, the PMOS transistor has a problem that its chip area is larger than that of an NMOS transistor having the same current capacity.
On the other hand, when an NMOS transistor is used as an output transistor, the voltage obtained by adding the output voltage to the gate threshold voltage of the NMOS transistor is required as the drive voltage for the NMOS transistor. Accordingly, a proposal has been made in which in a series regulator wherein an NMOS transistor is used as an output transistor, a voltage stepped up from the input voltage is generated using a charge pump to securely obtain a drive power supply for the NMOS transistor, as disclosed in Japanese Patent Application Laid-Open Publication No. Hei 3-204012.
The circuit configuration of the series regulator disclosed in Japanese Patent Application Laid-Open Publication No. Hei 3-204012 is shown in FIG. 4. In FIG. 4, numeral 1 designates an input terminal. An input voltage Vin is applied to this input terminal 1.
Numeral 2 designates an output terminal. This output terminal 2 supplies an output voltage Vout to a load 3.
Numeral 4 designates an NMOS transistor serving as an output transistor. This NMOS transistor 4 is connected between the input terminal 1 and the output terminal 2.
Numeral 5 designates an amplifier. This amplifier 5 supplies a drive voltage to the gate terminal of the NMOS transistor 4.
Numeral 6 designates a reference voltage generating circuit. This reference voltage generating circuit 6 generates a reference voltage Vref and applies the generated reference voltage Vref to the non-inverting input terminal (+) of the amplifier 5.
Numeral 7 designates a resistor pair consisting of a series circuit of two voltage-dividing resistors. This resistor pair 7 divides the output voltage Vout, and the divided voltage is applied to the inverting input terminal (−) of the amplifier 5.
Numeral 9 designates a charge pump circuit. This charge pump circuit 9 generates a voltage stepped up from the input voltage Vin, and this stepped-up voltage is supplied to the amplifier 5 as a power supply voltage.
The operation of the series regulator shown in FIG. 4 will be described below. When the input voltage Vin is applied to the input terminal 1, the charge pump circuit 9 operates, and the voltage stepped up from the input voltage Vin is supplied to the amplifier 5. The NMOS transistor 4 is driven by the amplifier 5, and the output voltage Vout is output from the output terminal 2. The output voltage Vout is negatively fed back to the amplifier 5 through the resistor pair 7. The amplifier 5 controls the NMOS transistor 4 so that the divided voltage of the output voltage Vout, being output from the resistor pair 7, becomes equal to the reference voltage Vref of the reference voltage generating circuit 6. As a result, the output voltage Vout is controlled so as to be stabilized.
Even if the difference between the input voltage Vin to the series regulator and the output voltage Vout from the series regulator becomes small owing to the reduction in the input voltage Vin, the amplifier 5 is biased by the voltage stepped up from the input voltage Vin. Hence, the amplifier 5 can supply a sufficiently high gate voltage to the NMOS transistor 4.
However, the conventional charge pump circuit 9 described above is connected only to the input voltage Vin, the ground and the amplifier 5. In this connection configuration, the stepped-up voltage with reference to the input voltage is used as the power supply voltage for the amplifier 5. For this reason, when the input voltage is sufficiently higher than the output voltage, the voltage is excessively high as the power supply voltage for the control drive circuit, and power consumption increases. In other words, in the configuration of the output circuit of the conventional series regulator described above, the drive voltage to the NMOS transistor 4 serving as an output transistor can be obtained securely. However, conversely, when the input voltage Vin is high, the voltage stepped up by the charge pump circuit 9 is high, and the power consumption in the amplifier 5 increases. Furthermore, in the case of a power amplifier, the output voltage of which is changed, it is necessary to sufficiently drive the output transistor even when the difference between the input and output voltages is small. However, since the difference between the input and output voltages is sufficient in most of the operation times, the above-mentioned increase in the power consumption in the amplifier 5 becomes further significant.